The present invention relates in general to cache memory and, in particular, to methods and apparatus for transferring cache block ownership.
In an effort to increase computational power, many computing systems are turning to multi-processor systems. A multi-processor system typically includes a plurality of microprocessors, a plurality of associated caches, and a main memory. In an effort to reduce bus traffic to the main memory, many multi-processor systems use a xe2x80x9cwrite-backxe2x80x9d (as opposed to a xe2x80x9cwrite-throughxe2x80x9d) policy. A xe2x80x9cwrite-backxe2x80x9d policy is a cache procedure whereby a microprocessor may locally modify data in its cache without updating the main memory until the cache data needs to be replaced. In order to maintain cache coherency in such a system, a cache coherency protocol may be used.
In an effort to further reduce bus traffic to the main memory, many of these cache coherency protocols allow a first cache that is holding locally modified data (i.e., xe2x80x9cdirtyxe2x80x9d data) to directly supply a second cache that is requesting the same block, without updating main memory. Typically, the first cache then puts its memory block in an xe2x80x9cownedxe2x80x9d state to indicate that the block is xe2x80x9cdirtyxe2x80x9d and shared. However, when the xe2x80x9cownedxe2x80x9d block is replaced, the first cache must write the block back to main memory so that the modifications are not lost. This write-back generates bus traffic to the main memory. Bus traffic increase memory latency and power consumption. Subsequent modifications to the memory block in the second cache will also need to be written-back to main memory, thereby generating additional bus traffic.